Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding for DSP Applications

Published on 04 Mar 2021. Written by Divyansh Jain

Overview: A enormous number of multiplications with coefficients that don’t alter during the strangulation of Digital Signal Processing (DSP) and intermedia applications like Fast Fourier Transform (FFT) and audio/video pamphlets whose toted out it. The optimized architecture block of the multiplier is very necessary because this is the vital component for realizing computationally protracted applications and it’s influenced complete system performance.

By the use of Canonic Signed Digit (CSD) delineation, regular coefficients can be ciphered to enclose the least non-zero values. CSD multipliers cover the slightest non-zero fractional products which in turn reduces their switching motion. Folding technique is a very important process to decrease the silicon area by time manifold.

Although the CSD multipliers are compact wired to explicit coefficients, functional blocks like adders and subtractor are not profitable to it. Since the explicit products formation unit is produced uniquely for a group of coefficients and cannot be rephrased for another group, this multiplier design misses flexibility.

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SLNOTE
Modified Booth (MB) encoding undertakes the previous restrictions and decreases to half the number of explicit products outcoming to the decreased area, analytical delay and power expenditure. Nonetheless, the faithful encoding circuit is needed and implicit products procreation is quite complex. Through this approach, the encoding circuitry of MB multiplier is erased.

We encode the coefficients off-line depend on the MB encoding and stock the MB encoded coefficients like 3 bits/ symbol into a ROM as the value of fixed coefficients are treated earlier. The derived NR4SD encoding process benefits one of the important value sets: {-1, 0, 1, 2} or {-2, -1, 0, 1}. The derived NR4SD encoding utilises four symbol numbers and its pre encoding multipliers contain a minimal complex implicit product formation circuit.

SLLATEST
Procedure: The modified booth (MB) algorithm is the extravagant radix-4 encoding process which is formulated as

B=j=0k-1bjMB22j …………………………...... (1)

Where bjMB is the element of {-2, -1, 0, 1, 2}; 0 ≤ j ≤ k-1 and it is formed as-

bjMB=-2b2j+1+b2j+b2j-1 ………………… (2)

Where b-1 = 0 and every MB symbol is showed by the bits s, one and two. The evaluation of MB symbols is given as –

bjMB=(-1)sj.(onej+2twoj) ………………… (3)

There are two types of Non-Redundant Radix-4 Signed Digit (NR4SD) algorithms which is given below –

• NR4SD- Algorithm: The stepwise procedure of this algorithm is given as below –

• Examine the original values j = 0 and c0 = 0.

• Evaluate the value of carrying and sum for inputs b2j and c2j which is given as

c2j+1=b2jc2j and n2j+=b2jc2j …………………. (4)

1. Evaluate the signed carry with positive nature and signed sum with negative nature of HA for inputs b2j+1 (+) and c2j+1 (+) which is given as 

c2j+2=b2j+1c2j+1 and n2j+1-=b2j+1c2j+1 ……… (5)

1. Evaluate the value of the final digit which is formulated as –

bjNR-=-2n2j+1-+n2j+ …………….. (6)

• NR4SD+ Algorithm: The step by step procedure of this algorithm is quite similar to NR4SD algorithm. The main difference is that the final digit evaluation step which is given as –

bjNR+=2n2j+1+-n2j- …………………… (7)

Conclusion: By off-line encoding of the typical coefficients, the novel designs of a pre-encoded multiplier are tested and feeding them in system memory. The derived pre-encoded NR4SD multiplier devices are ambient area and contain productive power factor than earlier multiplier designs.

SLDYK
Kit required to develop Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding for DSP Applications:

• Digital Signal Processing

Technologies you will learn by working on Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding for DSP Applications:

• Digital Signal Processing

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