Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes

Published on 19 Apr 2022. Written by Divyansh Jain

Error Correction Codes (ECCs) recommends a delayed penalty in pervading the data as encoding or decoding has to be executed. ECCs are extensively used to conserve memory and to bypass data corruption. Due to hindering the use of ECCs in high-speed memories, it led to the use of Single Error Correction Double Error Detection (SECDED) codes. 

Multiple Cell Upsets (MCUs) becomes more familiar and restrict the use of SEC-DED codes unless they are joined with interleaving as technology scaled up. The biggest issue in memories is arising the errors which can be explained i.e. by radiation-induced soft errors that alter one or more memory cells, shift their values and other deficiencies cause permanent damage. 

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SLNOTE
Error Correction Checks add some supplementary parity check bits to particular memory word, so detection and correction of errors can smoothly happen which leads to shortening the effective capacity of memory. ECC circuitry has struck on the delay as the data has to concealed when writing on the memory and decoded when reading on it. SEC-DED codes have a minimal Hamming distance of four such that single bit errors can be corrected and double errors are not is corrected.

SEC-DED can be mixed with interleaving to assure that the errors involve with one bit per logical word. ECCs can be classified into following-

1. Bose-Choudhuri-Hocquenghem (BCH) codes.
2. Euclidian Geometry.
3. Difference Set.
4. Orthogonal Latin Squares.
5. Reed-Solomon (RS) codes.

SLLATEST
In SEC-RS codes, the codeword is level-headed by adjoined two check symbols to a data word of K symbols. Let, G matrix [G] = [IK P] where IK is the K×K identity matrix and P is of dimension K×2.

Process: RS codes are a position of non-binary BCH codes formulated with symbols from a Galois Field GF (q) where q is typically a power of two. For q = 2m, m bit symbols are used to form the code. RS codes contain the following parameters:

Maximum block length n = q – 1

Number of parity check symbols n-k = 2t

Minimum distance dmin = 2t +1, when t = 1, the minimum distance is 3.

The parity check matrix for an RS code is given as

H=[1111212t4t2] ……………………………… (1)

Where α = primitive element in GF(q).

The decoding of SEC-RS code initiates with the computation of syndrome vector which is given below

s=H. r ……………………………………… (2)

When a single symbol error e in position i in the block, the syndrome would be 

s=[ee.i] …………………………………… (3)

Established extension of SEC-RS code to allow approaching the minimum block length up to q + 1 symbols, the design matrix is given as

H={111?1210n-11} ……………….. (4)

The columns of H are uniformly independent.

The derived SEC-RS codes are conferred to minimize the delay for encoding and error correction. Two types of SEC-RS codes are given as below-

• Optimize Parity Check Matrix: The alteration to RS codes dabs to balance the involvement of both calculations, which is given as follows

H={11-2111?3-n-110101} …… (5)

• Extension to Longer Block Lengths: The delay of RS encoders and decoders is the capacity of the Galois Field that is used to compose the code which is given as below

H={111111211? 121? 112100010}001 … (6)

Where α = Primitive element in GF (n).

Conclusion: Due to alteration of Single Error Correction Reed Solomon (SEC-RS) codes have been scheduled with the even-handed of decreasing delay. The derived codes implement momentous delay cutback in both propagation delays.

SLDYK
Kit required to develop Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes:

• VLSI

Technologies you will learn by working on Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes:

• VLSI Design
• Electric
• Electronic

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