An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm

Published on 19 Apr 2022. Written by Divyansh Jain

Overview: In any digital signal processing, image and video processing, wireless communication and biomedical signal processing systems, the Finite Impulse Response (FIR) filter contains broad ranges of applications like Software Defined Radio (SDR) and manifold classic video codecs. A sanctioned finite impulse response (FIR) filter with emphatically acquirable filter coefficients, installation factors and spaces which may alter according to the stipulation of distinct standards in a compact computing scheme to verify it.

A powerful reformable FIR filter with momentous changes can trigger the system inventor to evolve the chip with minimal cost, power and area as well as the proficiency to engage at ultra-high speed. The multiplier is the leading constraint in any finite impulse response (FIR) filter which describes the enforcement of the aimed filter.

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SLNOTE
Multiple Constant Multiplication (MCM) is the type of operation which provides multiplication between one peculiar variable (input) and various coefficients. This process can be divided into 2 algorithms which are given as

1. Graph related algorithm.
2. Common subsystem elimination (CSE) algorithm.

SLLATEST
CSE algorithm is quite beneficial for modern systems. MCM scheme algorithms are not applicable for an application like Software Defined Radio (SDR) system through the exertion of FIR filter. SDR system is different from basic algorithms due to obvious reasons which are given as below:

1. Based on the demand of distinct standards, the collective factors of filters in software defined radio (SDR) systems are emphatically programmable.
2. In SDR system, the urgency of extraordinary computationally skilful platforms occurred for these algorithms.

The technique which recommends the view of waiving the natural sub-expression in binary form is called the Binary common subexpression elimination (BCSE) algorithm. This algorithm is useful for intriguing a capable constant multiplier and it is useful for decomposable FIR filters with minimal complexity. The main concern with this algorithm is that the incremental adder step and costing of hardware part create the inadequacy of the device.

Procedure: BCSE algorithm can be classified into two types which are given as –

1. Horizontal BCSE algorithm exploits CSs showing within particular coefficients to dispose of extravagant computations.
2. Vertical BCSE algorithm utilizes CSs organized across bordering coefficients to get rid of extravagant computations.

In the BCSE algorithm, the number of BCSs steps = 2n – (n + 1)

Where n = binary number bit size.

The 3-bit BCSE algorithm is expressed as

X*H=X12+X116+X1128+X11024+X18192+X65536 ……………………………. (1)

The 2-bit BCSE algorithm is expressed as

X*H=X12+X18+X132+X1128+X1512+X12048+X18192+X132768 ……………. (2)

From the complexity study, the BCSE algorithm contains two key factors which is:

The first one is Adder Cost (AC) which is defined as the number of adders needed to equipment the FIR filter. The adder cost for 3-bit BCSE algorithm is given as –

AC = (18/3) – 1 = 5 units of adder.

For 2-bit BCSE algorithm, AC = (16/2) – 1 = 7 units of adder.

Another factor is the Adder Step (AS) which is defined as the logarithmic incrementation of adder cost of the individual adder. The adder step for 3-bit BCSE algorithm is given as –

AS = [log23] + [log2 (16/3)] = 2 + 3 = 5

For 2-bit BCSE algorithm, AS = [log22] + [log2 (16/2)] = 1 + 3 = 4

Hence the explanation of BCSE algorithm calculations.

Conclusion: Through the handling of Binary common subexpression elimination (BCSEs) of distinct lengths horizontally to distinctive layers of the shift and add related continual multiplier structure, another elimination of CSs step. The derived VHBCSE algorithm shows the efficiency advancement in the ADP step is 28% and 81.6% in PDP step.

SLDYK
Kit required to develop An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm:

• VLSI

Technologies you will learn by working on An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm:

• VLSI Design

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